Analog Circuit Design and Verification

Supported by the National Science Foundation (NSF grant #CCR9971168), Professor Myers and his colleagues demonstrated the viability of analog architectures for MAP decoders. This project led to the design of the first successful analog MAP decoder using strictly CMOS design. The fabricated chip was tested at bit rates of 1 Mb/s to 10 Mb/s with a typical power consumption of only 16uW.  Under NSF CCF award 1117515, Professor Myers in collaboration with Professor Peng Li of Texas A&M integrated research in the area of analog circuit verification with analog testing, and applying this work to the challenges of modern analog circuit designs that include extensive digital components. During this project, we continued to develop our LEMA verification tool including improvements to our model generation tool, a new verification property language for analog/mixed-signal circuits, and new verification methods.  This work built upon past projects supported by the Semiconductor Research Corporation and additional support from Intel Corporation.



  • Satish Batchu (MS), Qualcomm, Raleigh, NC.
  • Jie Dai (PhD), Director of IP Dept. in Brite Semiconductor (Shanghai) Corporation.
  • Andrew Fisher (PhD), Sandia National Laboratories, Albuquerque, NM.
  • Kevin Jones (BS), Aberdeen Proving Ground, Philadelphia, PA.
  • Dhanashree Kulkarni (MS), Intel Corporation, Hillsboro, OR.
  • Scott Little (PhD), Freescale, Austin, TX.
  • Nick Seegmiller (BS),, Park City, UT.
  • Robert Thacker (PhD), IBM Austin, TX.
  • David Walter (PhD), Associate Professor, Virginia State University, Petersburg, VA.
  • Hao Zheng (PhD), Associate Professor, University of South Florida.


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