PhD Dissertations:

• Tramy Nguyen, Asynchronous Genetic Circuit Design, PhD Dissertation, University of Utah, December 2019
• Leandro Watanabe, Scalable and Reproducible Modeling and Simulation for Heterogeneous Populations, PhD Dissertation, University of Utah, May 2019
• Zhen Zhang, Verification Methodologies for Fault-Tolerant Network-on-Chip Systems , PhD Dissertation, University of Utah, May, 2016.
• Andrew N. Fisher, Efficient, Sound Formal Verification for Analog/Mixed-Signal Circuits , PhD Dissertation, University of Utah, August, 2015.
• Nicholas Roehner, Technology Mapping of Genetic Circuits Designs , PhD Dissertation, University of Utah, December, 2014.
• Curtis K. Madsen, Stochastic Analysis of Synthetic Genetic Circuits , PhD Dissertation, University of Utah, August, 2013.
• Robert Thacker, A New Verification Method For Embedded Systems , PhD Dissertation, University of Utah, December, 2009.
• Scott Little, Efficient Modeling and Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets , PhD Dissertation, University of Utah, December, 2008.
• Hiroyuki Kuwahara, Model Abstraction and Temporal Behavior Analysis of Genetic Regulatory Networks , PhD Dissertation, University of Utah, December, 2007.
• Nathan Barker, Learning Genetic Regulatory Network Connectivity from Time Series Data , PhD Dissertation, University of Utah, December, 2007.
• David C. Walter, Verification of Analog and Mixed-Signal Circuits Using Symbolic Methods , PhD Dissertation, University of Utah, August, 2007.
• Curtis A. Nelson, Technology Mapping of Timed Asynchronous Circuits , PhD Dissertation, University of Utah, December, 2004.
• Hans Jacobson, Interlocked Synchronous Pipelines , PhD Dissertation, University of Utah, May, 2004.
• Eric Mercer, Correctness and Reduction in Timed Circuit Analysis , PhD Dissertation, University of Utah, December, 2002.
• Jie Dai, Design Methodology for Analog VLSI Implementations of Error Control Decoders , PhD Dissertation, University of Utah, December, 2002.
• Eric Peskin, Protocol Selection, Implementation, and Analysis for Asynchronous Circuits , PhD Dissertation, University of Utah, August, 2002.
• Hao Zheng, Modular Synthesis and Verification of Timed Circuits Using Automatic Abstraction, PhD Dissertation, University of Utah, August, 2001.
• Wendy Belluomini, Algorithms for Synthesis and Verification of Timed Circuits and Systems, PhD Dissertation, University of Utah, September, 1999.
• Chris J. Myers, Computer Aided Synthesis and Verification of Gate-Level Timed Circuits, PhD Dissertation, Stanford University, October, 1995.

Master’s Theses:

• Meher Samineni, Software Compliance Testing For Workflows Using the Synthetic Biology Open Language, MS Thesis, University of Utah, May, 2019.
• Michael Zhang, SBOLExplorer: Data Infrastructure and Data Mining for Genetic Design Repositories, MS Thesis, University of Utah, May, 2019.
• Dhanashree Kulkarni, Improved model generation and property specification for analog/mixed-signal circuits , MS Thesis, University of Utah, August, 2013.
• Satish Batchu, Automatic Extraction of Behavioral Models from Simulations of Analog/Mixed-Signal (AMS) Circuits , MS Thesis, University of Utah, December, 2010.
• Nam Nguyen, Design and Analysis of Genetic Circuits , MS Thesis, University of Utah, August, 2008.
• Yanyi Zhao, Application of Synchronous Synthesis Tools for High-Level Asynchronous Design , MS Thesis, University of Utah, December, 2004.
• Chris Krieger, Complete State Coding of Timed Asynchronous Circuits, MS Thesis, University of Utah, December 2002.
• Kip Killpack, Analysis and Characterization of a Locally-Clocked Module, MS Thesis, University of Utah, May 2002.
• Eric G Mercer, Stochastic Cycle Period Analysis in Timed Circuits, MS Thesis, University of Utah, May 1999.
• Brandon M. Bachman, Architectural-Level Synthesis of Asynchronous Systems, MS Thesis, University of Utah, December 1998.
• Robert A. Thacker, Implicit Methods for Timed Circuit Synthesis, MS Thesis, University of Utah, June, 1998.
• Hao Zheng, Specification and Compilation of Timed Systems, MS Thesis, University of Utah, June, 1998.

Bachelor’s Theses:

• Z. Zundel, Improving Authentication and Authorization on SynBioHub, BS Thesis, University of Utah, December 2019
• M. Zhang, SBOLDesigner: A Hierarchical Genetic Design Editor, BS Thesis, University of Utah, April 2018
• M. Samineni, Software Compliance Testing for the Synthetic Biology Open Language, BS Thesis, University of Utah, August 2017
• L. Watanabe, Hierarchical Stochastic Simulation of Genetic Circuits, BS Thesis, University of Utah, May, 2014.
• K. Jones, Automated Abstraction of Labeled Petri Nets, BS Thesis, University of Utah, May, 2011.
• T. Patterson, Modeling and Visualization of Synthetic Genetic Circuits, BS Thesis, University of Utah, May, 2011.
• C. Madsen, Representing Genetic Networks as Labeled Hybrid Petri Nets for State Space Exploration and Markov Chain Analysis, BS Thesis, University of Utah, June, 2009.
• S. Little, A Comparison of Timed State Space Analysis Methods, BS Thesis, University of Utah, June, 2003.
• Y. Zhao, Design of an Asynchronous Ditherer for an MPEG Decoder, BS Thesis, University of Utah, June, 2003.