Supported by grants from the National Science Foundation (NSF CAREER award MIP-9625014), Intel Corporation, the Semiconductor Research Corporation (SRC), and the State of Utah, Professor Myers and his graduate students developed the ATACS tool for the synthesis and verification of timed asynchronous circuits. ATACS was utilized during the Intel RAPPID project which resulted in a prototype VLSI chip that was 3 times faster while using only half the power of the comparable synchronous design. NSF Japan Program award INT-0087281 helped foster a collaboration between the PI and Professor Tomohiro Yoneda of the National Institute of Informatics in Tokyo which has resulted in over 30 publications to date.

Faculty:

• Chris J. Myers, Professor, University of Utah
• Tomohiro Yoneda, Professor, National Institute of Informatics, Tokyo, Japan

Alumni:

• Brandon Bachman (MS), Intel Corporation, Folsom, CA.
• Wendy Belluomini (PhD), IBM Almaden, San Jose, CA.
• Jeff Cuthbert (BS), Raytheon, Dallas, TX.
• Hans Jacobson (PhD), IBM Yorktown, NY.
• Sung-Tae Jung (PostDoc), Professor, Wonkwang University, Korea.
• Kip Killpack (MS), Intel Corporation, Hillsboro, OR.
• Christopher Krieger (MS), Intel Corporation, Fort Collins, CO.
• Eric Mercer (PhD), Associate Professor, Brigham Young University, Provo, UT.
• Curt Nelson (PhD), Professor, Walla Walla University, Walla Walla, WA.
• John Perry (BS), JPMorgan, New York City, NY.
• Eric Peskin (PhD), Center for Health Informatics and Bioinformatics, New York, NY.
• Allen Sjogren (BS), Hart Scientific, Salt Lake City, UT.
• Robert Thacker (PhD), IBM Austin, TX.
• Yanyi Zhao (MS), Stryker, San Jose, CA.
• Hao Zheng (PhD), Associate Professor, University of South Florida.

Software:

• ATACS

Books:

• Chris J. Myers, Asynchronous Circuit Design, John Wiley & Sons, July, 2001.
• Chris J. Myers (translated by T. Yoneda), Asynchronous Circuit Design (in Japanese), Kyoritsu Shuppan, September, 2003.
• Chris J. Myers (translated by Li), Asynchronous Circuit Design (in Chinese), Tsinghua University Press, September, 2013.

PhD Dissertations:

• Curtis A. Nelson, Technology Mapping of Timed Asynchronous Circuits , PhD Dissertation, University of Utah, December, 2004.
• Hans Jacobson, Interlocked Synchronous Pipelines , PhD Dissertation, University of Utah, May, 2004.
• Eric Mercer, Correctness and Reduction in Timed Circuit Analysis , PhD Dissertation, University of Utah, December, 2002.
• Eric Peskin, Protocol Selection, Implementation, and Analysis for Asynchronous Circuits , PhD Dissertation, University of Utah, August, 2002.
• Hao Zheng, Modular Synthesis and Verification of Timed Circuits Using Automatic Abstraction, PhD Dissertation, University of Utah, August, 2001.
• Wendy Belluomini, Algorithms for Synthesis and Verification of Timed Circuits and Systems, PhD Dissertation, University of Utah, September, 1999.
• Chris J. Myers, Computer Aided Synthesis and Verification of Gate-Level Timed Circuits, PhD Dissertation, Stanford University, October, 1995.

Master’s Theses:

• Yanyi Zhao, Application of Synchronous Synthesis Tools for High-Level Asynchronous Design , MS Thesis, University of Utah, December, 2004.
• Chris Krieger, Complete State Coding of Timed Asynchronous Circuits, MS Thesis, University of Utah, December 2002.
• Kip Killpack, Analysis and Characterization of a Locally-Clocked Module, MS Thesis, University of Utah, May 2002.
• Eric G Mercer, Stochastic Cycle Period Analysis in Timed Circuits, MS Thesis, University of Utah, May 1999.
• Brandon M. Bachman, Architectural-Level Synthesis of Asynchronous Systems, MS Thesis, University of Utah, December 1998.
• Robert A. Thacker, Implicit Methods for Timed Circuit Synthesis, MS Thesis, University of Utah, June, 1998.
• Hao Zheng, Specification and Compilation of Timed Systems, MS Thesis, University of Utah, June, 1998.

Bachelor’s Theses:

• S. Little, A Comparison of Timed State Space Analysis Methods, BS Thesis, University of Utah, June, 2003.
• Y. Zhao, Design of an Asynchronous Ditherer for an MPEG Decoder, BS Thesis, University of Utah, June, 2003.

Journal Publications:

• N. Hamada, Y. Shiga, T. Konishi, H. Saito, T. Yoneda, C. Myers, and T. Nanya, A behavioral synthesis system for asynchronous circuits with bundled-data implementation, in IPSJ Transactions on System LSI Design Methodology, Vol. 2, 64-79, February, 2009.
• H. Saito, N. Hamada, N. Jindapetch, T. Yoneda, C. Myers, and T. Nanya, Scheduling methods for asynchronous circuits in bundled-data implementation based on the approximation of start times, in IEICE Transactions, E90-A(12): 2790-2799, December, 2007.
• T. Yoneda and C. Myers, Synthesis of timed circuits based on decomposition, in IEEE Transactions on CAD, 26(7): 1177-1195, July, 2007.
• C. Nelson, C. Myers, and T. Yoneda, Efficient verification of hazard-freedom in gate-level timed asynchronous circuits, in IEEE Transactions on CAD, 26(3): 592-605, March, 2007.
• H. Zheng, C. Myers, D. Walter, S. Little, and T. Yoneda, Verification of timed circuits with failure directed abstractions, in IEEE Transactions on CAD, 25(3): 403-412, March, 2006.
• T. Kitai, T. Yoneda, and C. Myers, Failure trace analysis of timed circuits for automatic timing constraints derivation, in IEICE Transactions, E88-D(11): 2555-2564, November, 2005.
• D. Pradubsuwun, T. Yoneda, and C. Myers, Partial order reduction for detecting safety and timing failures of timed circuits, in IEICE Transactions, E88-D(7): 2555-2564, July, 2005.
• T. Kitai, Y. Oguro, T. Yoneda, E. Mercer, and C. Myers, Partial order reduction for timed circuit verification based on a level oriented model, in IEICE Transactions, E86-D(12): 2601-2611, 2003.
• H. Zheng, E. Mercer, and C. Myers, Modular verification of timed circuits using automatic abstraction, in IEEE Transactions on CAD, 22(9):1138-1153, September, 2003.
• T. Yoneda, E. Mercer, and C. Myers, Modular Synthesis of Timed Circuits using Partial Order Reduction, in IEICE Transactions, E85-A(12): 2684-2692, 2002.
• H. Jacobson and C. J. Myers, Efficient algorithms for exact two-level hazard-free logic minimization, in IEEE Transactions on CAD, 21(11): 1269-1283, November, 2002.
• S. T. Jung and C. J. Myers, Direct synthesis of timed circuits from free-choice STGs, in IEEE Transactions on CAD, 21(3): 275-290, March, 2002.
• B. Zhou, T. Yoneda, and C. Myers, Framework of Timed Trace Theoretic Verification Revisited, in IEICE Transactions, E85-D(10): 1595-1604, 2002.
• K. Stevens, S. Rotem, R. Ginosar, P. A. Beerel, C. J. Myers, K. Yun, R. Kol, C. Dike, and M. Roncken, An Asynchronous Instruction Length Decoder, in IEEE Journal of Solid State Circuits, 36(2): 217-228, February, 2001.
• W. Belluomini and C. J. Myers, Timed circuit verification using TEL structures, in IEEE Transactions on CAD, 20(1): 129-146, January, 2001.
• A. E. Sjogren and C. J. Myers, Interfacing synchronous and asynchronous modules within a high-speed pipeline, in IEEE Transactions on VLSI Systems, 8(5): 573-583, October, 2000.
• W. J. Belluomini and C. J. Myers, Timed state space exploration using POSETs, in IEEE Transactions on CAD, 19(5), May, 2000.
• C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng, POSET timing and its application to the synthesis and verification of gate-level timed cirucits, in IEEE Transactions on CAD, 18(6), June, 1999.
• P. A. Beerel, C. J. Myers, and T. H.-Y. Meng, Covering conditions and algorithms for the synthesis of speed-independent circuits, in IEEE Transactions on CAD, 17(3), March, 1998.
• C. J. Myers and T. H.-Y. Meng, Synthesis of timed asynchronous circuits (figures), in IEEE Transactions on VLSI Systems, 1(2), June, 1993 (invited paper).

Patents:

• R. Ginosar, R. Kol, K. Stevens, P. Beerel, K. Yun, C. Myers, and S. Rotem, Branch instruction handling in a self-timed marking system, issued August 3, 1999, patent number 5,931,944.
• R. Ginosar, R. Kol, K. Stevens, P. Beerel, K. Yun, C. Myers, and S. Rotem, Efficient self-timed marking of lengthy variable length instructions, issued August 24, 1999, patent number 5,941,982.
• R. Ginosar, R. Kol, K. Stevens, P. Beerel, K. Yun, C. Myers, and S. Rotem, Apparatus and method for self-timed marking of variable length instructions having length-affecting prefix bytes, issued September 7, 1999, patent number 5,948,096.
• R. Ginosar, R. Kol, K. Stevens, P. Beerel, K. Yun, C. Myers, and S. Rotem, Apparatus and method for parallel processing and self-timed serial marking of variable length instructions , issued November 2, 1999, patent number 5,978,899.

Conference and Workshop Papers:

• F. Butzke, C. Myers, M. Moreira, and N. Calazans, “QDI logic for signaling data validity in bundled-data design: a kogge-stone case study,” in 2014 International Symposium on Asynchronous Circuits and Systems, May, 2014.
• N. Hamada, Y. Shiga, T. Konishi, H. Saito, T. Yoneda, C. Myers, and T. Nanya, A behavioral synthesis system for asynchronous circuits with bundled-data implementation, in The 8th International Conference on Application of Concurrency to System Design, June, 2008.
• F. Beal, T. Yoneda, and C. Myers, Hazard checking of timed asynchronous circuits revisited, in 7th International Conference on Applications of Concurrency to System Design, July, 2007.
• H. Saito, N. Jundapetch, T. Yoneda, C. Myers, and T. Nanya, ILP-based scheduling for asynchronous circuits in bundled-data implementations, in 2005 Int. Conf. on Computer and Information Technology, September, 2006.
• H. Saito, N. Jundapetch, T. Yoneda, C. Myers, and T. Nanya, A scheduling method for asynchronous bundled-data implementations based on the completion of data operations, in 2005 Int. Tech. Conf. on Circuits/Systems, Computers, and Communication, July, 2005.
• H. Saito, N. Jundapetch, T. Yoneda, and C. Myers, A scheduling method for asynchronous bundled-data implementations, in 2005 Int. Workshop on Logic Synthesis, June, 2005.
• T. Yoneda, A. Matsumoto, M. Kato, and C. Myers, High level synthesis of timed asynchronous circuits, in The Eleventh International Symposium on Asynchronous Circuits and Systems, March, 2005.
• D. Pradubsuwun, T. Yoneda, and C. Myers, Partial order reduction for detecting safety and timing failures of timed circuits, in Automated Technology for Verification and Analysis, November, 2004.
• T. Yoneda, H. Onda, and C. Myers Synthesis of speed-independent circuits based on decomposition, in The Tenth International Symposium on Asynchronous Circuits and Systems, April, 2004.
• C. Nelson, C. Myers, and T. Yoneda, Efficient verification of hazard-freedom in gate-level timed asynchronous circuits, in 2003 International Conference on Computer-Aided Design, November, 2003.
• H. Zheng, C. Myers, D. Walter, S. Little, and T. Yoneda, Verification of timed circuits with failure directed abstractions, in IEEE International Conference on Computer Design, October, 2003.
• C. Myers, E. Mercer, and H. Jacobson, Verifying synchronization strategies, in Formal Methods for Globally Asynchronous Locally Synchronous (GALS) Architecture, September, 2003 (invited paper).
• T. Kitai, Y. Oguro, T. Yoneda, E. Mercer, and C. Myers, Level oriented formal model for asynchronous circuit verification and its efficient analysis method, in 2002 Pacific Rim International Symposium on Dependable Computing, pages 210-218, November, 2002.
• T. Yoneda, T. Kitai, and C. Myers, Automatic derivation of timing constraints by failure analyis, in Computer Aided Verification (CAV ’02), pages 195-208, July, 2002.
• E. Mercer, C. J. Myers, T. Yoneda, and H. Zheng, Modular synthesis of timed circuits using partial orders on LPNs, in Theory and Practice of Timed Systems, TPTS ’02, April, 2002.
• H. Jacobson, P. Kudva, P. Bose, P. Cook, S. Schuster, E. Mercer, and C. J. Myers,Synchronous interlocked pipelines, in The Eighth International Symposium on Asynchronous Circuits and Systems, pages 3-12, April, 2002.
• B. Zhou, T. Yoneda, C. Myers, Framework of timed trace theoretic verification revisited, in The Tenth Asian Test Symposium, November, 2001.
• T. Yoneda, E. Mercer, and C. Myers, Modular synthesis of timed circuits using partial order reduction, in The Tenth Workshop on Synthesis and System Integration of MIxed Technologies (SASIMI 2001), October, 2001.
• E. Mercer, C. Myers, and T. Yoneda, Improved POSET timing analysis in timed Petri nets, in The Tenth Workshop on Synthesis and System Integration of MIxed Technologies (SASIMI 2001), October, 2001.
• H. Zheng, E. Mercer, and C. Myers, Automatic abstraction for verification of timed circuits and systems, in Computer Aided Verification (CAV), pages 182-193, July, 2001.
• K. Killpack, E. Mercer, C. J. Myers A standard-cell self-timed multiplier for power and area critical synchronous systems, in 2001 Advanced Research in VLSI Conference, pages 188-201, March, 2001.
• C. Myers and H. Jacobson, Efficient exact two-level hazard-free logic minimization, in The Seventh International Symposium on Asynchronous Circuits and Systems, pages 64-73, March, 2001 (best paper finalist).
• C. Myers, W. Belluomini, K. Killpack, E. Mercer, E. Peskin, and H. Zheng, Timed Circuits: A New Paradigm for High-Speed Design, in 2001 Asia and South Pacific Design Automation Conference, February, 2001 (invited paper).
• H. Zheng and C. J. Myers, Automatic Abstraction for Synthesis and Verification of Deterministic Timed Systems, in 2000 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, December, 2000.
• H. Jacobson, C. Myers, and G. Gopalakrishnan, Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines, in 2000 International Conference on Computer-Aided Design, November, 2000.
• E. G. Mercer and C. J. Myers, Stochastic Cycle Period Analysis in Timed Circuits, in Proc. International Symposium on Circuits and Systems(ISCAS), May, 2000.
• S. T. Jung and C. J. Myers, Direct Synthesis of Timed Asynchronous Circuits, in IEEE International Conference on Computer Aided Design (ICCAD), November, 1999.
• B. M. Bachman, H. Zheng, and C. J. Myers, Architectural Synthesis of Timed Asynchronous Systems, in IEEE International Conference on Computer Design (ICCD), October, 1999.
• E. G. Mercer and C. J. Myers, Stochastic Cycle Period Analysis in Timed Circuits , in 1999 International Workshop on Logic Synthesis, July, 1999.
• S. T. Jung and C. J. Myers, Direct Synthesis of Timed Asynchronous Circuits, in 1999 International Workshop on Logic Synthesis, July, 1999.
• S. Rotem, K. Stevens, R. Ginosar, P. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, M.Roncken, and B. Agapiev, RAPPID: An Asynchronous Instruction Length Decoder,” in The Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, April, 1999 (best paper award).
• W. Belluomini, C. J. Myers and H. P. Hofstee Verification of Delayed Reset Domino Circuits using ATACS,” in The Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, April, 1999.
• W. Belluomini, C. J. Myers, and H. P. Hofstee Verification of Delayed Reset Domino Circuits using ATACS, in 1999 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March, 1999.
• R. Thacker, W. Belluomini, and C. J. Myers Timed Circuit Synthesis using Implicit Methods,” in 1999 12th VLSI Design Conference, January, 1999.
• W. Belluomini and C. J. Myers Verification of Timed Systems using POSETs,” in Computer Aided Verification (CAV), June, 1998.
• W. Chou, P. A. Beerel, R. Ginosar, R. Kol, C. J. Myers, S. Rotem, K. Stevens, and K. Y. Yun, Average-case optimized technology mapping of one-hot domino circuits, in The Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems, April, 1998.
• W. Belluomini and C. J. Myers, Timed Event/Level Structures, in 1997 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, December, 1997.
• A. E. Sjogren and C. J. Myers, Interfacing synchronous and asynchronous modules within a high-speed pipeline, in 17th Conference on Advanced Research in VLSI, September, 1997.
• R. A. Thacker and C. J. Myers, Synthesis of timed circuits using BDDs, in 1997 International Workshop on Logic Synthesis, May, 1997.
• C. J. Myers and H. Zheng, An asynchronous implementations of the MAXLIST algorithm, in 1997 International Conference on Acoustics, Speech, and Signal Processing, April, 1997.
• W. Belluomini and C. J. Myers, Efficient timing analysis algorithms for timed state space exploration, in The Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, April, 1997.
• C. J. Myers, P. A. Beerel, and T. H.-Y. Meng, Technology mapping of timed circuits, in 2nd Working Conference on Asynchronous Design Methodologies, June, 1995.
• C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng, Automatic synthesis of gate-level timed circuits with choice, in Chapel Hill Conference on Advanced Research in VLSI, March, 1995.
• T. G. Rokicki and C. J. Myers, Automatic verification of timed circuits, in Computer Aided Verification (CAV), June, 1994.
• C. J. Myers and T. H.-Y. Meng, Synthesis of timed asynchronous circuits, in IEEE International Conference on Computer Design (ICCD), October, 1992.