Conference / Workshop Papers

 

• C. Myers, G. Bader, P. Gleeson, M. Golebiewski, M. Hucka, N. Le Novere, D. Nickerson, F. Schreiber, and D. Waltemath, A Brief History of COMBINE, in 2017 Winter Simulation Conference, December, 2017.
• V. Dubikhin, D. Sokolov, C. Myers, A. Mokhov, and, A. Yakovlev, Model discovery for analog/mixed-signal circuits, in 2017 Frontiers in Analog CAD Workshop, July, 2017.
• V. Dubikhin, C. Myers, D. Sokolov, I. Syranidis, and, A. Yakovlev, INVITED: Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems, in 2017 Design Automation Conference, June, 2017.
• A. Fisher, C. Myers, and P. Li, Reachability analysis using extremal rates, in 7th Nasa Formal Methods Symposium, April, 2015.
• Z. Zhang, W. Serwe, J. Wu, T. Yoneda, H. Zheng, and C. Myers, Formal analysis of a fault-tolerant routing algorithm for a network-on-chip, in 19th International Workshop on Formal Methods for Industrial Critical Systems, September, 2014.
• A. Fisher, S. Batchu, K. Jones, D. Kulkarni, S. Little, D. Walter, and C. Myers, LEMA: a tool for the formal verification of digitally-intensive analog/mixed-signal circuits, in 2014 Midwest Symposium on Circuits and Systems, August, 2014.
• F. Butzke, C. Myers, M. Moreira, and N. Calazans, “QDI logic for signaling data validity in bundled-data design: a kogge-stone case study,” in 2014 International Symposium on Asyn- chronous Circuits and Systems, May, 2014.
• L. Watanabe and C. Myers, Hierarchical stochastic simulation of genetic circuits, in 2014 Symposium on Theory of Modeling and Simulation, April, 2014.
• D. Kulkarni, A. Fisher, and C. Myers, A new assertion property language for analog/mixed- signal circuits, in 2013 Forum on Design Languages, September, 2013 (best paper candidate).
• H. Lin, P. Li, and C. Myers, Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis, to appear in 2013 Design Automation Conference, June, 2013.
• N. Miskov-Zivanov, J. Faeder, C. Myers, and H. Sauro, Modeling and design automation of biological circuits and systems, in 2012 International Conference on Computer-Aided Design, November, 2012 (invited).
• H. Zheng, A. Price, and C. Myers, Using decision diagrams to compactly represent state space for explicit model checking, in 2012 IEEE International High Level Design Validation and Test Workshop, November, 2012.
• Y. Zhang, E. Rodriguez, H. Zheng, and C. Myers, An improvement in partial order reduction using behavioral analysis, in IEEE Computer Society Annual Symp. on VLSI, August, 2012.
• H. Zheng, E. Rodriguez, Y. Zhang, and C. Myers, A compositional minimization approach for large asynchronous design verification, in 19th International SPIN Workshop on Model Checking of Software, July, 2012.
• C. Madsen, C. Myers, N. Roehner, C. Winstead, and Z. Zhang, Utilizing stochastic model checking to analyze genetic circuits, in 2012 Computational Intelligence in Bioinformatics and Computational Biology, May, 2012 (best student paper).
• D. Kulkarni, S. Batchu, and C. Myers, Improved model generation of AMS circuits for formal verification, in 2011 Virtual Worldwide Forum for PhD Researchers in Electronic Design Automation, November, 2011.
• J.Wu, Z.Zhang, and C.Myers, A fault-tolerant routing algorithm for anetwork-on-chip using a link fault model, in 2011 Virtual Worldwide Forum for PhD Researchers in Electronic Design Automation, November, 2011.
• H. Kuwahara and C. Myers, Erlang-delayed stochastic chemical kinetic formalism for efficient analysis of biological systems with non-elementary reaction effects, in 2011 ACM Conference on Bioinformatics, Computational Biology, & Biomedicine, August, 2011.
• H. Yao, H. Zheng, and C. Myers, State space reductions for scalable verification of asynchronous designs, in 2010 IEEE International High Level Design Validation and Test Work- shop, November, 2010.
• C. Winstead, C. Madsen, and C. Myers, iSSA: an incremental stochastic simulation algorithm for genetic circuits, in 2010 International Conference on Circuits and Systems, May, 2010.
• R. Thacker, K. Jones, C. Myers, and H. Zheng, Automatic abstraction for verification of cyber-physical systems, in The 1st ACM/IEEE International Conference on Cyber-Physical Systems, April, 2010.
• C. Myers, N. Barker, H. Kuwahara, K. Jones, C. Madsen, and N. Nguyen, Genetic design automation, in 2009 International Conference on Computer-Aided Design, November, 2009 (invited).
• R.Thacker, C. Myers, K. Jones, and S. Little, A New Verification Method For Embedded Systems, in IEEE International Conference on Computer Design, October, 2009.
• S. Little and C. Myers, Abstract modeling and simulation aided verification of analog/mixed-signal cirucits, in The Workshop on Formal Verification of Analog Circuits, July, 2008.
• N. Nguyen, N. Barker, H. Kuwahra, C. Madsen, and C. Myers, Synthesis of genetic circuits from graphical specifications, in 2008 Int. Workshop on Logic Synthesis, June, 2008 (invited).
• N. Hamada, Y. Shiga, T. Konishi, H. Saito, T. Yoneda, C. Myers, and T. Nanya, A behavioral synthesis system for asynchronous circuits with bundled-data implementation, in The 8th International Conference on Application of Concurrency to System Design, June, 2008.
• S. Little, A. Sen, and C. Myers, Application of automated model generation techniques to analog/mixed-signal circuits, in 8th International Workshop on Microprocessor Test and Verification, December, 2007.
• S. Little, D. Walter, K. Jones, and C. Myers, Analog/mixed-signal circuit verification using models generated from simulation traces, in Automated Technology for Verification and Analysis, October, 2007.
• D. Walter, S. Little, and C. Myers, Bounded model checking of analog and mixed-signal circuits using an SMT solver, in Automated Technology for Verification and Analysis, October, 2007.
• F. Beal, T. Yoneda, and C. Myers, Hazard checking of timed asynchronous circuits revisited, in 7th International Conference on Applications of Concurrency to System Design, July, 2007.
• H. Kuwahara and C. Myers, Production-passage-time approximation: a new approximation method to accelerate the simulation process of enzymatic reactions, in The Elventh Annual International Conference on Research in Computational Molecular Biology, April, 2007.
• N. Nguyen, H. Kuwahara, C. Myers, and J. Keener, The design of a genetic Muller C-element, in The Thirteenth International Symposium on Asynchronous Circuits and Systems, March, 2007 (best paper).
• D. Walter, S. Little, N. Seegmiller, C. Myers, and T. Yoneda, Symbolic model checking of analog/mixed-signal circuits, in 2007 Asia and South Pacific Design Automation Conference, January, 2007.
• S. Little, N. Seegmiller, D. Walter, C. Myers, and T. Yoneda, Verification of analog/mixed-signal circuits using labeled hybrid Petri nets, in 2006 International Conference on Computer-Aided Design, November, 2006.
• H. Saito, N. Jundapetch, T. Yoneda, C. Myers, and T. Nanya, ILP-based scheduling for asynchronous circuits in bundled-data implementations, in 2005 Int. Conf. on Computer and Information Technology, September, 2006.
• H. Kuwahara, C. Myers, and M. Samoilov, Abstracted stochastic analysis of type 1 pili expression in E. coli, to appear at The 2006 International Conference on Bioinformatics and Computational Biology, June, 2006.
• N. Barker, C. Myers, and H. Kuwahara, Learning genetic regulatory network connectivity from time series data, to appear at The 19th International Conference on Industrial, Engineering, and Other Applications of Applied Intelligent Systems (IEA/AIE’06), June, 2006.
• H. Saito, N. Jundapetch, T. Yoneda, C. Myers, and T. Nanya, A scheduling method for asynchronous bundled-data implementations based on the completion of data operations, in 2005 Int. Tech. Conf. on Circuits/Systems, Computers, and Communication, July, 2005.
• H. Saito, N. Jundapetch, T. Yoneda, and C. Myers, A scheduling method for asynchronous bundled-data implementations, in 2005 Int. Workshop on Logic Synthesis, June, 2005.
• H. Kuwahara, C. Myers, N. Barker, M. Samoilov, and A. Arkin, Asynchronous abstraction methodology for genetic regulatory networks, in The Third International Workshop on Computational Methods in Systems Biology, April, 2005.
• C. Myers, R. Harrison, D. Walter, N. Seegmiller, and S. Little, The case for analog circuit verification , in The Workshop on Formal Verification of Analog Circuits, April, 2005.
• T. Yoneda, A. Matsumoto, M. Kato, and C. Myers, High level synthesis of timed asynchronous circuits, in The Eleventh International Symposium on Asynchronous Circuits and Systems, March, 2005.
• S. Little, D. Walter, N. Seegmiller, C. Myers, and T. Yoneda, Verification of analog and mixed-signal circuits using timed hybrid Petri nets, in Automated Technology for Verification and Analysis, November, 2004.
• D. Pradubsuwun, T. Yoneda, and C. Myers, Partial order reduction for detecting safety and timing failures of timed circuits, in Automated Technology for Verification and Analysis, November, 2004.
• T. Yoneda, H. Onda, and C. Myers Synthesis of speed-independent circuits based on decomposition, in The Tenth International Symposium on Asynchronous Circuits and Systems, April, 2004.
• C. Nelson, C. Myers, and T. Yoneda, Efficient verification of hazard-freedom in gate-level timed asynchronous circuits, in 2003 International Conference on Computer-Aided Design, November, 2003.
• H. Zheng, C. Myers, D. Walter, S. Little, and T. Yoneda, Verification of timed circuits with failure directed abstractions, in IEEE International Conference on Computer Design, October, 2003.
• C. Myers, E. Mercer, and H. Jacobson, Verifying synchronization strategies, in Formal Methods for Globally Asynchronous Locally Synchronous (GALS) Architecture, September, 2003 (invited paper).
• T. Kitai, Y. Oguro, T. Yoneda, E. Mercer, and C. Myers, Level oriented formal model for asynchronous circuit verification and its efficient analysis method, in 2002 Pacific Rim International Symposium on Dependable Computing, pages 210-218, November, 2002.
• T. Yoneda, T. Kitai, and C. Myers, Automatic derivation of timing constraints by failure analyis, in Computer Aided Verification (CAV ’02), pages 195-208, July, 2002.
• C. Winstead, J. Dai, S. Yu, R. Harrison, C. Myers, and C. Schlegel, Analog decoding of product codes, in International Symposium on Information Theory, June, 2002.
• J. Dai, C. J. Winstead, C. J. Myers, R. R. Harrison, and C. Schlegel, Cell library for automatic synthesis of analog error control decoders, in Proc. International Symposium on Circuits and Systems(ISCAS), pages 481-484, May, 2002.
• E. Mercer, C. J. Myers, T. Yoneda, and H. Zheng, Modular synthesis of timed circuits using partial orders on LPNs, in Theory and Practice of Timed Systems, TPTS ’02, April, 2002.
• H. Jacobson, P. Kudva, P. Bose, P. Cook, S. Schuster, E. Mercer, and C. J. Myers,Synchronous interlocked pipelines, in The Eighth International Symposium on Asynchronous Circuits and Systems, pages 3-12, April, 2002.
• B. Zhou, T. Yoneda, C. Myers, Framework of timed trace theoretic verification revisited, in The Tenth Asian Test Symposium, November, 2001.
• T. Yoneda, E. Mercer, and C. Myers, Modular synthesis of timed circuits using partial order reduction, in The Tenth Workshop on Synthesis and System Integration of MIxed Technologies (SASIMI 2001), October, 2001.
• E. Mercer, C. Myers, and T. Yoneda, Improved POSET timing analysis in timed Petri nets, in The Tenth Workshop on Synthesis and System Integration of MIxed Technologies (SASIMI 2001), October, 2001.
• C. Winstead, C. Myers, C. Schlegel, and R. Harrison, Analog decoding of product codes, in 2001 IEEE Information Theory Workshop, pages 131-133, September, 2001.
• H. Zheng, E. Mercer, and C. Myers, Automatic abstraction for verification of timed circuits and systems, in Computer Aided Verification (CAV), pages 182-193, July, 2001.
• C. Winstead, J. Dai, W. J. Kim, S. Little, Y.-B. Kim, C. Myers, and C. Schlegel Analog MAP Decoder for (8,4) Hamming code in subthreshold CMOS, in International Symposium on Information Theory, June, 2001.
• K. Killpack, E. Mercer, C. J. Myers A standard-cell self-timed multiplier for power and area critical synchronous systems, in 2001 Advanced Research in VLSI Conference, pages 188-201, March, 2001.
• C. Winstead, J. Dai, W. J. Kim, S. Little, Y.-B. Kim, C. Myers, and C. Schlegel Analog MAP Decoder for (8,4) Hamming code in subthreshold CMOS, in 2001 Advanced Research in VLSI Conference, pages 132-147, March, 2001.
• C. Myers and H. Jacobson, Efficient exact two-level hazard-free logic minimization, in The Seventh International Symposium on Asynchronous Circuits and Systems, pages 64-73, March, 2001 (best paper finalist).
• C. Myers, W. Belluomini, K. Killpack, E. Mercer, E. Peskin, and H. Zheng, Timed Circuits: A New Paradigm for High-Speed Design, in 2001 Asia and South Pacific Design Automation Conference, February, 2001 (invited paper).
• H. Zheng and C. J. Myers, Automatic Abstraction for Synthesis and Verification of Deterministic Timed Systems, in 2000 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, December, 2000.
• H. Jacobson, C. Myers, and G. Gopalakrishnan, Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines, in 2000 International Conference on Computer-Aided Design, November, 2000.
• E. G. Mercer and C. J. Myers, Stochastic Cycle Period Analysis in Timed Circuits, in Proc. International Symposium on Circuits and Systems(ISCAS), May, 2000.
• S. T. Jung and C. J. Myers, Direct Synthesis of Timed Asynchronous Circuits, in IEEE International Conference on Computer Aided Design (ICCAD), November, 1999.
• B. M. Bachman, H. Zheng, and C. J. Myers, Architectural Synthesis of Timed Asynchronous Systems, in IEEE International Conference on Computer Design (ICCD), October, 1999.
• E. G. Mercer and C. J. Myers, Stochastic Cycle Period Analysis in Timed Circuits , in 1999 International Workshop on Logic Synthesis, July, 1999.
• S. T. Jung and C. J. Myers, Direct Synthesis of Timed Asynchronous Circuits, in 1999 International Workshop on Logic Synthesis, July, 1999.
• S. Rotem, K. Stevens, R. Ginosar, P. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, M.Roncken, and B. Agapiev, RAPPID: An Asynchronous Instruction Length Decoder,” in The Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, April, 1999 (best paper award).
• W. Belluomini, C. J. Myers and H. P. Hofstee Verification of Delayed Reset Domino Circuits using ATACS,” in The Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, April, 1999.
• W. Belluomini, C. J. Myers, and H. P. Hofstee Verification of Delayed Reset Domino Circuits using ATACS, in 1999 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March, 1999.
• R. Thacker, W. Belluomini, and C. J. Myers Timed Circuit Synthesis using Implicit Methods,” in 1999 12th VLSI Design Conference, January, 1999.
• W. Belluomini and C. J. Myers Verification of Timed Systems using POSETs,” in Computer Aided Verification (CAV), June, 1998.
• W. Chou, P. A. Beerel, R. Ginosar, R. Kol, C. J. Myers, S. Rotem, K. Stevens, and K. Y. Yun, Average-case optimized technology mapping of one-hot domino circuits, in The Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems, April, 1998.
• W. Belluomini and C. J. Myers, Timed Event/Level Structures, in 1997 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, December, 1997.
• A. E. Sjogren and C. J. Myers, Interfacing synchronous and asynchronous modules within a high-speed pipeline, in 17th Conference on Advanced Research in VLSI, September, 1997.
• R. A. Thacker and C. J. Myers, Synthesis of timed circuits using BDDs, in 1997 International Workshop on Logic Synthesis, May, 1997.
• C. J. Myers and H. Zheng, An asynchronous implementations of the MAXLIST algorithm, in 1997 International Conference on Acoustics, Speech, and Signal Processing, April, 1997.
• W. Belluomini and C. J. Myers, Efficient timing analysis algorithms for timed state space exploration, in The Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, April, 1997.
• C. J. Myers, P. A. Beerel, and T. H.-Y. Meng, Technology mapping of timed circuits, in 2nd Working Conference on Asynchronous Design Methodologies, June, 1995.
• C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng, Automatic synthesis of gate-level timed circuits with choice, in Chapel Hill Conference on Advanced Research in VLSI, March, 1995.
• T. G. Rokicki and C. J. Myers, Automatic verification of timed circuits, in Computer Aided Verification (CAV), June, 1994.
• C. J. Myers and T. H.-Y. Meng, Synthesis of timed asynchronous circuits, in IEEE International Conference on Computer Design (ICCD), October, 1992.